计算机系统I-指令集体系结构

What is ISA

ISA(Instruction Set Architecture) is a part of the processor architecture.

ISA is defined group of commands and operations used by the software to communicate with the hardware.

What is RISC-V

RISC-V is an ISA standard, an open-source implementation of a reduced instruction set computing(RISC) based instruction set architecture(ISA).

Other ISAs like x86, arm are commercially protected by patents, preventing practical efforts to reproduce the computer systems.

RISC-V is open. It permits any person or group to construct compatible computers and uses associated software.

Goals in Defining RISC-V

A completely open ISA that is freely available to academia and industry. A real ISA suitable for direct native hardware implementation, not just simulation nor binary translation.

An ISA that avoids “over-architecting” for

• A particular microarchitecture style (e.g., microcode, hardwired control, in-order, decoupled, out-of-order) or
• Implementation technology (e.g., full-custom, ASIC, FPGA), but which allows efficient implementation in any of these.

RISC-V ISA includes a small base integer ISA, usable by itself as a base for customized accelerators or for educational purposes, and optional standard extensions, to support general-purpose software development.

RISC-V Principles

Generally kept very simple and extendable, whether short, long, or variable.

Separated into multiple specifications, like user-level ISA spec (compute instructions) or compressed ISA spec (16-bit instructions)

ISA support is given by RV + word-width + extensions supported. E.g., RV64I means 64-bit RISC-V with support for the Integer instruction set

User-Level ISA

Defines the normal instructions needed for computation.

• A mandatory base integer ISA
• • I: Integer instructions
  • • ALU
    • Branches/jumps
    • Loads/stores
• Standard extensions
• • M: Integer Multiplication and Division
  • A: Atomic Instructions
  • F: Single-Precision Floating-Point
  • D: Double-Precision Floating-Point
  • C: Compressed Instructions
  • G=IMAFD: integer base + four standard extensions

RV32I is a subset of RV64I.

RISC-V Processor State

Program counter (PC)

32 64-bit integer registers (x0-x31)

• x0 always contains a 0
• x1 to hold the return address on a call
• more…

32 floating-point (FP) registers (f0-f31)

• each can contain a single- or double-precision FP value (64-bit IEEE FP)

FP status register (fsr), used for FP rounding mode & exception reporting.

ALU Instructions

• add x1,x2,x3: regs[x1]<-regs[x2]+regs[x3]
• addi x1,x2,3: regs[x1]<-regs[x2]+3
• more…

Load/Store Instructions

• ld x1,80(x2): regs[x1]<-mem[80+regs[x2]]
• lbu x1,40(x3): regs[x1]<-$_{64}0^{56}\#\#mem[40+regs[x3]]$
• more…

Control Transfer Instructions

• jal x1,offset: regs[x1]<-PC+4; PC<-PC + (offset<<1)
• more…

Four Core RISC-V Instruction Formats

31-25	24-20	19-15	14-12	11-7	6-0	type
funct7	rs2	rs1	funct3	rd	opcode	R-type
imm[11:0]		rs1	funct3	rd	opcode	I-type
imm[11:5]	rs2	rs1	funct3	imm[4:0]	opcode	S-type
imm[12,10:5]	rs2	rs1	funct3	imm[4:1,11]	opcode	B-type
imm[20,10:1,11,19:12]				rd	opcode	J-type
imm[31:12]				rd	opcode	U-type

RISC-V Hybrid Instruction Encoding

16, 32, 48, 64, … bits length encoding

Base instruction set (RV32) always has fixed 32-bit instructions with lowest to bits = $11_2$

All branches and jumps have targets at 16-bit granularity (even in base ISA where all instructions are fixed 32 bits)

ALU Instructions: R-Type

R-type (Register)

• rs1 and rs2 are the source register, rd is the destination
• ADD/SUB
• ADDW/SUBW: add and sub in word
• more…
• 0000000 src2 src1 ADD dest OP

ALU Instructions: I-Type

I-type (immediate), all immediates in all instructions are sign extended.

• ADDI: adds sign extended 12-bit immediate to rs1
• STLI: set less than immediate
• more…

Load/Store Instructions: I/S-Type

Load instruction: lw, ld, lwu (I-type)

• rd = mem (rs1+imm)

Store instruction: sw,sd,swu (S-type)

• mem (rs1 + imm) = rs2

ALU Instructions: U-Type

LUI/AUIPC: load upper immediate/add upper immediate to PC

• U-immediate[32:12] dest LUI

Writes 20-bit immediate to top of destination register, used to build large immediates

Control Transfer Instructions: J-Type

Unconditional jumps: PC + offset target

• JAL: jump and link, also writes PC + 4 to x1, J-type

Control Transfer Instructions: B-Type

Conditional branches: B-type and PC + offset targer

Where is NOP

ADDI x0,x0,0

31-25	24-20	19-15	14-12	11-7	6-0
imm[11:0]		rs1	funct3	rd	opcode
12		5	3	5	7
0		0	ADDI	0	OP-IMM

## Privileged ISA: Modes

RISC-V privileged spec defines 3 levels of privilege, called modes.

Machine mode is the highest privileged mode and the only required mode

Level	Encoding	Name	Abbreviation
0	00	User/Application	U
1	01	Supervisor	S
2	10	Reserved
3	11	Machine	M

Processors typically spend most of their execution time in their least-privileged mode, interrupts and exceptions transfer control to more-privileged modes.